ATEN=0, AET=0, AJD=0, ASEN=0, AST=Others
Common Control Register 4
| CMPD | Compare Match Data |
| ASEN | Adjust receive sampling timing enable 0 (0): Adjust sampling timing disable. 1 (1): Adjust sampling timing enable. |
| ATEN | Adjust transmit timing enable 0 (0): Adjust transmit timing disable. 1 (1): Adjust transmit timing enable. |
| AST | Adjustment value for receive Sampling Timing 0 (000): 1TCLK delay 0 (Others): Setting prohibited 1 (001): 2TCLK delay 2 (010): 3TCLK delay 3 (011): 4TCLK delay |
| AJD | Adjustment Direction for receive sampling timing 0 (0): The sampling timing is adjusted backward to the middle of bit. 1 (1): The sampling timing is adjusted forward to the middle of bit. |
| ATT | Adjustment value for Transmit timing |
| AET | Adjustment edge for transmit timing 0 (0): When CCR1.TINV is 0, adjust the rising edge timing. When CCR1.TINV is 1, adjust the falling edge timing. 1 (1): When CCR1.TINV is 0, adjust the falling edge timing. When CCR1.TINV is 1, adjust the rising edge timing. |